QUESTION
Create a block that check if a number is divisible by “5” ?
Every cycle, LSB receives a new bit; if the current sequence is divisible by “5”, block transmits “1”.
RTL
module Div_5 (clk,
rst,
d_in,
d_out,
remainder
);
//COLLEGE OF VLSI
input clk, rst, d_in;
output reg [2:0] remainder;
output reg d_out;
parameter IDLE=3'd0, REM1=3'd1,REM2=3'd2, REM3=3'd3, REM4=3'd4, REM0=3'd5;
reg [2:0] pr_state, nxt_state;
always @(posedge clk , negedge rst)
begin
if(!rst==1) begin
pr_state <= IDLE;
d_out <= 1'd0;
end
else
pr_state <= nxt_state;
end
always @(pr_state, d_in)
begin
case(pr_state)
IDLE : begin
if(d_in==0) begin
nxt_state <= IDLE;
end
else begin
nxt_state <= REM1;
end
d_out <= 1'b0;
remainder <=3'd0;
end
REM1 : begin
if(d_in==0) begin
nxt_state <= REM2;
end
else begin
nxt_state <= REM3;
end
d_out <= 1'b0;
remainder <= 3'd1;
end
REM2 : begin
if(d_in==0) begin
nxt_state <= REM4;
end
else begin
nxt_state <= REM0;
end
d_out <= 1'b0;
remainder <= 3'd2;
end
REM3 : begin
if(d_in==0) begin
nxt_state <= REM1;
end
else begin
nxt_state <= REM2;
end
d_out <= 1'b0;
remainder <= 3'd3;
end
REM4 : begin
if(d_in==0) begin
nxt_state <= REM3;
end
else begin
nxt_state <= REM4;
end
d_out <= 1'b0;
remainder <= 3'd4;
end
REM0 : begin
if(d_in==0) begin
nxt_state <= REM0;
end
else begin
nxt_state <= REM1;
end
d_out <= 1'b1; //output is high
remainder <= 3'd0;
end
endcase
end
endmodule
//COLLEGE OF VLSI
TESTBENCH
`timescale 1ns / 1ps
module tb();
//COLLEGE OF VLSI
reg clk, rst, d_in;
wire [2:0] remainder;
wire d_out;
Div_5 dut(clk,
rst,
d_in,
d_out,
remainder
);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
rst = 1'b0; d_in = 1'b0;
@(posedge clk);
rst = 1'b1;
repeat(20) begin
@(posedge clk);
d_in = $random;
end
$finish;
end
endmodule
//COLLEGE OF VLSI
WAVEFORM
STATE DIAGRAM
DIV BY 5
Appreciated
Thankyou