QUESTION Design the Digital Circuit which gives fout = (2/3) fin. SLOUTION A frequency divider circuit is a digital circuit that takes an input clock signal and produces an output clock signal with a lower frequency. It is commonly used
SOP CIRCUIT
QUESTION Design A SOP circuit to detect the decimal number from 5 to 10 in a 4-bit GRAY Code input. DESIGN RTL TESTBENCH Will update soon.. WAVEFORM Will update soon..
Fibonacci series
Fibonacci series The Fibonacci series is a sequence of numbers in which each number is the sum of the two preceding ones, usually starting with 0 and 1. So, the Fibonacci series begins as follows: 0, 1, 1, 2, 3,
DIV BY 5
QUESTION Create a block that check if a number is divisible by “5” ? Every cycle, LSB receives a new bit; if the current sequence is divisible by “5”, block transmits “1”. RTL TESTBENCH WAVEFORM STATE DIAGRAM
FIFO
Synchronous FIFO In Verilog, you can implement a FIFO data structure using a combination of registers and logic gates. Here’s an example of how you can implement a simple FIFO module in Verilog: RTL TESTBENCH